Background Information: 

David Keezer received the B.S. degree from the University of California, Berkeley, CA, USA, the M.S. degree from the California Institute of Technology, Pasadena, CA, USA, the Ph.D. degree from Carnegie-Mellon University, Pittsburgh, PA, USA, and the M.B.A. degree from the Florida Institute of Technology, Melbourne, FL, USA., He was an Associate Professor with the University of South Florida, Tampa, FL, USA. He was with Harris Corporation, Englewood, CO, USA, Intel Corporation, Santa Clara, CA, USA, and IBM Corporation, Armonk, NY, USA. He joined the Georgia Institute of Technology, Atlanta, GA, USA, in 1995, where he was a Professor of electrical and computer engineering. He has authored over 200 articles on electronics testing. His current research interests include the design and test of high-performance electronic systems.

Research Field:

test methods for high performance electronic systems, design of high speed logic systems, and advanced electronics packaging methods

Educational Background:

•1983: Ph.D. Electrical Engineering Carnegie-Mellon University 

•1979: M.S. Applied Physics California Institute of Technology

•1985: Master of Business Administration (MBA) Florida Institute of Technology

•1978: B.A. Physics and Applied Mathematics University of California at Berkeley

Work Experience:

•Now, Eastern Institute of Technology, Chair Professor

•2004 to 2022 Georgia Institute of Technology, Professor of Electrical Engineering & Computer Engineering (Promoted, 2004) 

•1995-2004 Georgia Institute of Technology, Associate Professor of Electrical Engineering & Computer Engineering (Tenured, 1999), Electrical Test Thrust Leader for the NSF Packaging Research Center 1995-2004. 

•1989-1995 University of South Florida, Associate Professor of Electrical Engineering (Tenured, 1995) Joint appointment in the Center for Microelectronics Research and the Department of Electrical Engineering. 

•1988-1989 Harris Corporation, Government Systems Sector, Advanced Component Test Laboratory Group Leader / Staff Engineer, Directed a group of 25 engineers and a $10M electronics testing laboratory.

•1986-1987 Harris Corporation, Government Systems Sector, Test Technology Group Leader / Staff Engineer 

Managed a group of 6 engineers developing test methods for VHSIC and VLSI devices.

•1983-1985 Harris Corporation, Government Systems Sector, Associate Principal Engineer, Developed test methods for VHSIC and VLSI.

•Summer 1981 IBM Corp. Research Laboratories, San Jose, Calif, Academic Associate, Pre-doctoral Fellow, 

Designed and analyzed the dynamic performance of ion-implanted magnetic bubble memory device structures.

•Summer 1980 IBM Corp. Research Laboratories, San Jose, Calif. Academic Associate, Pre-doctoral Fellow 

Developed stroboscopic laser techniques for analysis of magnetic bubble memories.

•Summer 1977 Intel Corp., Santa Clara, California. Laboratory Assistant. Supported experimentation on electronics packaging materials.

Awards and Honors:

IEEE Fellow, January 1, 2010

Citation: “for contributions to the advancement of high-speed digital test technology.”

Representative Works:

Published Books and Parts of Books

[1] “Neural Network Clock Distribution” D.C. Keezer, V.K. Jain, Silicon Architectures for Neural Nets, (Ed. M. Sami), pages 101-112, North-Holland Publisher, 1990. 

[2] “Technologies for Restructuring of VLSI and WSI Systems” D.C. Keezer, R.A. Lee, V.K. Jain, Contributed section in Defect and Fault Tolerance in VLSI Systems, Vol. 3, (Ed. by T. Mangir), pages162-174, 1991. 

[3] “Yield, Testing, and Reliability” D.C. Keezer, Chapter 11 in Thin Film Technology Handbook, (A.Elshabini-Riad Editor), pp. 11-1 through 11-50, McGraw-Hill, Inc., December 1997. ISBN#0-07-019025-9. 

[4] “Fundamentals of Electrical Test” (Chapter 19), pages748-779 in Fundamentals of Electronics Packaging, 

Rao Tummala editor, ISBN 0-07-137169-9. This chapter is co-authored with Prof. Bruce Kim (Arizona State Univ.) and Sasidhar Koppolu (Intel Corp.) Prof. Keezer is the lead author. The chapter manuscript was completed in 2000, was revised and published in 2001 by McGraw Hill. It is a widely used textbook for courses in electronics packaging. 

[5] "Electrical Test of SOP Modules and Systems," Chapter 12, pages 659-714 in Introduction to System-on-Package (SOP), Rao Tummala and Madhavan Swaminathan, et al. S.S. Akbay, S. Bhattacharya, D.C. Keezer, and A. Chatterjee authored Chapter 12. Publ. 2008 McGraw-Hill Co. - ISBN 978-0-07145906-8. Original manuscript was completed in 2006, edited in 2007/08, and published in 2008.

Refereed Journal Publications

[1] “Annihilation of Vertical Bloch Lines During Creep in Magnetic Bubble Materials” B.S. Han, D.C. Keezer, F.B. Humphrey, J. of Applied Physics, Vol. 53, No. 3, pp. 2549-2551, March 1982. Also presented at the Conf. on Magnetism and Magnetic Materials, Atlanta, Georgia, Nov. 1981. 

[2] “Modeling of Transfer Gates in Ion-Implanted Bubble Devices” D.C. Keezer, P. Asselin, F.B. Humphrey, 

IEEE Trans. on Magnetism, MAG-18, No. 6, pp.1361-1363, Nov. 1982. Also presented at the 3rd Joint Intermag - Magnetism and Magnetic Materials Conf., Montreal, Canada, July 1982. 

[3] “Stretching of Stripe Domains in Ion-Implanted Channels” D.C. Keezer, F.B. Humphrey, IEEE Trans. on Magnetism, MAG-18, No. 6, pp. 1367-1369, Nov. 1982. 

Also presented at the 3rd Joint Intermag-Magnetism and Magnetic Materials Conf., Montreal, Canada, July 1982. 

[4] “Wafer Scale Integration: A University Perspective” V.K. Jain, D.L. Landis, D.C. Keezer, K.T. Wilson, and D. Whittaker, Intl. J. of VLSI Signal Processing, Vol. 2, pp. 253-270, May 1991. 

[5] “An Architecture for WSI Rapid Prototyping” V.K. Jain, H. Hikawa, D.C. Keezer, IEEE Computer, pp. 71-75, April 1992.

[6] “Fault Isolation and Performance Characterization of High-Speed Digital Multichip Modules” D.C. Keezer, 

IEEE Trans. on Components, Packaging, and Manufacturing Technology (CPMT-B), Vol. 18, No. 4, pp. 614-619, November 1995. 

[7] “Energy Dispersive X-Ray Spectroscopy Characterization of Tape-Automated Bond Metallurgical Interfaces to 

Silicon Microcircuits” D.C. Keezer, J. Rates, SCANNING (The Journal of Scanning Microscopy), Vol. 18, No. 3, pp. 218-219, April 1996. 

[8] “Systematic Logic Fault Isolation Using Voltage-Contrast and Critical-Path Tracing” D.C. Keezer, SCANNING (The Journal of Scanning Microscopy), Vol. 19, No. 3, pp. 192-193, April 1997. 

[9] “Transmission Line Transient Analysis in Lossy Dispersive MCM Technologies” R.J. Wenzel, D.C. Keezer, 

Intl. Journal of Microcircuits and Electronic Packaging, Vol. 20, No. 2, pp. 187-195, June 1997.