Background Information: 

Dr. Yajun Yu obtained her B.Sc in 1994 and Ph.D degrees in 2004 from Zhejiang University and National University of Singapore, respectively.  Currently, she is a teaching professor in the Easten Institute of Technology, Ningbo, China, meanwhile serving as the deputy director for academic affairs.  She has been an instructor, assistant professor and teaching associate professor in Zhejiang University, Nanyang technological University and Southern University of Science and Technology (SUSTech), respectively. Her research focused on VLSI (Very Large Scale Integration) signal processing.  She has published more than 30 papers in the top international journals and served as an associate editor for several international journals. Since joining SUSTech, she has mainly engaged in teaching and conducts courses in the areas of Electronics and Information Engineering, including Digital Signal Processing, Digital Electronics, Digital Image Processing, Digital System Design, etc. She has extensive experience in the accreditation for Engineering Education.

Educational Background:

2000 – 2004 PhD  (ElecEng) – National University of Singapore, Singapore

1994 – 1997 MEng (BiomedEng) – Zhejiang University, PRChina 

1989 – 1994 BSc  (BiomedEng) – Zhejiang University, PRChina 

Work Experience:

06.2024 - : Teaching Professor, Deputy Director for Academic Affairs, Easten Institute of Technology, Ningbo, China

08.2016 –06.2024: Teaching Associate Professor, Southern University of Science and Technology, Shenzhen, China

12.2005 – 02.2016: Assistant Professor, Nanyang Technological University, Singapore

01.2004 – 11.2005: Research Fellow, Nanyang Technological University, Singapore

05.1998 – 01.2004: Research Engineer, National University of Singapore, Singapore

07.1997 – 04.1998: Instructor, Zhejiang University, Hangzhou, PRC

Academic Experience:

07.2009 – 07.2009: Visiting Professor, Curtin University of Technology, Perth, Australia

10.2002 – 07.2003: Visiting Researcher, Hong Kong Polytechnic University, Hong Kong, PRC

06.2002 – 09.2002: Visiting Researcher, Tampere University of Technology, Tampere, Finland

Academic Part-time Jobs (Partial):

2016 – 2018 Associate Editor, IEEE Trans. on Circuits and System I. 

2015 – 2017 Associate Editor, Digital Signal Processing, Elsevier

2010 – 2013 Associate Editor, IEEE Trans. on Circuits and Systems II. 

2009 – 2017 Associate Editor, Circuit Systems and Signal Processing.

2007 – 2009 Co-Guest Editor, Circuits Systems and Signal Processing, special issue on “Low Power Digital Filter Design Techniques and Their Applications”, Jan. 2010.

2018 – 2019 Treasurer, IEEE CAS Shenzhen Chapter Committee

2006 – 2016 Treasurer/Secretary/Deputy Chair, IEEE CAS Singapore Chapter Committee

2007 – now Member, IEEE Circuits and Systems Society, DSP Technical Committee.

Awards and Honors:

2023, the first prize of the Southern China Division and the third prize of the national level, in the 10th National competition of Universities on the design of Experimental Case projects for the fundamental Courses in the Electrical and Electronics Engineering, the only participant.

2020,  the second prize of the Provincial Teaching Achievement Award， “Student-oriented and aptitude-based teaching  - the exploration and practice of cultivating innovative talents in communication majors”. Ranking 7. 

Representative Works:

1. W. B. Ye and Y. J. Yu, “Two-step Optimization Approach for the Design of Multiplierless Linear-Phase FIR Filters”, IEEE Trans. Circuits, Syst. I., vol. 62, no. 5, pp. 1279-1287, May 2015. (Invited paper for special issue of IEEE TCAS-I on best papers selected from ISCAS’14.)

2. X. Lou, Y. J. Yu and P. K. Meher, “Fine-Grained Critical Path Analysis and Optimization for Area-Time Efficient Realization of Multiple Constant Multiplications”, IEEE Trans. Circuits, Syst. I., vol. 62, no. 3, pp. 863-872, March 2015.

3. W. B. Ye, and Y. J. Yu, “Single Stage and Cascade Design of High Order Multiplierless linear phase FIR Filters Using Genetic Algorithm”, IEEE Trans. Circuits, Syst. I., vol. 60, no. 11, pp. 2987-2997, Nov. 2013. (Invited paper for special issue of IEEE TCAS-I on best papers selected from ISCAS’12.)

4. Y. J. Yu, and W. J. Xu, “Mixed-Radix Fast Filter Bank Approach for the Design of Variable Digital Filters with Simultaneously Tunable Bandedge and Fractional Delay”, IEEE Trans. Signal Processing, vol. 60, no. 1, pp.100-111, Jan. 2012.

5. D. Shi, and Y. J. Yu, “Design of Discrete-valued Linear Phase FIR Filters in Cascade Form”, IEEE Trans. Circuits, Syst. I. vol. 58, no. 7, pp.1627-1636, July 2011. (Invited paper for special issue of IEEE TCAS-I on best papers selected from ISCAS’10.)

6. D. Shi, and Y. J. Yu, “Design of Linear Phase FIR Filters with High Probability of Achieving Minimum Number of Adders”, IEEE Trans. Circuits, Syst. I. vol. 58, no. 1, pp. 126-136, Jan. 2011.

7. Y. J. Yu, and Y. C. Lim, “Optimization of Linear Phase FIR Filters in Dynamically Expanding Subexpression Space”, Circuit Syst. Signal Process, vol. 29, no. 1, pp. 65-80, Feb. 2010.

8. Y. J. Yu, D. Shi, and Y. C. Lim, “Design of Extrapolated Impulse Response FIR Filters with Residual Compensation in Subexpression Space”, IEEE Trans. Circuits, Syst. I, vol. 56, no. 12, pp. 2621-2633, Dec. 2009.

9. Y. J. Yu, Y. C. Lim and D. Shi, “Low Complexity Design of Variable Bandedge Linear Phase FIR filters with Sharp Transition Band”, IEEE Trans. Signal Processing, vol. 57, no. 4, pp. 1328-1338, April 2009.  

10. Y. J. Yu and Y. C. Lim, “Design of Linear Phase FIR Filters in Subexpression Space Using Mixed Integer Linear Programming”, IEEE Trans. Circuits, Syst. I, vol. 54, no. 10, pp. 2330-2338, Oct. 2007.